The present invention relates to semiconductor integrated circuits and, more particularly, to a circuit for measuring the phase margin and loop gain of a phase-locked loop.
A typical PLL includes a phase/frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO) and a frequency divider. The VCO generates a clock signal with a phase and frequency that is a function of the voltage applied to the oscillator. The phase/frequency detector detects a phase difference between the VCO output and the input signal. The phase/frequency detector generates a phase control signal as a function of the difference and applies the phase control signal to the charge pump, which increases or decreases the voltage across the loop filter. This voltage is applied to the VCO for controlling the oscillation frequency and phase. Once a PLL has locked a feedback signal onto the phase and frequency of a reference input signal, any remaining phase error between the reference feedback signal and the input signal is known as "jitter".
The performance of a second order PLL can be defined in terms of a damping factor (.zeta.) and an un-damped natural frequency (.omega..sub.n). These performance characteristics determine the phase margin (.phi..sub.m) and the loop gain (K) for the PLL. In integrated circuit applications, it is important that these performance characteristics lie within predefined specifications. However, the phase margin and loop gain can vary by as much as a factor of two or more from one integrated circuit to the next due to variations in process, supply voltage and temperature, which are known as "PVT". Variations in the phase margin and loop gain that exceed specified margins can lead to difficulties in clock synchronization, accurate recovery of serial data streams and other functions commonly performed by PLLs.